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DS3105

108

9.4

JTAG Test Registers

IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An

optional test register, the identification register, has been included in the device design. It is used with the IDCODE

instruction and the Test-Logic-Reset state of the TAP controller.

Bypass Register. This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to

provide a short path between JTDI and JTDO.

Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells

and digital I/O cells. The BSDL file is available on the DS3105 page of Microsemi’s website.

Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is

selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device

identification code for the DS3105 is shown in Table 9-2.

Table 9-2. JTAG ID Code

DEVICE

REVISION

DEVICE CODE

MANUFACTURER CODE

REQUIRED

DS3105

Consult factory

0000000010100011

00010100001

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